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Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs


Synopsis          Three dimensional integration is one of the promising solutions to check the bare 3D integrated circuits before utilizing in the applications. In the existing system design of an heterogeneous architecture is being evaluated using low power silicon redundancy schemes. The technique is b..

Design of Adiabatic Quantum-Flux-Parametron Register Files using a Top-Down Design Flow


Synopsis                                Electricity usage in global data centers is estimated 200 terawatts hour (TWh) each year, or about 1% of the total electricity consumed. This significant amount of en..

Test-Friendly Data-Selectable Self-Gating (DSSG)


Abstract◦        Clock networks consume large amounts of dynamic power,Clock gating is a common method for dynamic power reduction, and XOR self-gating is one of the useful clock gating methods for reducing meaningless clock toggling to provide extreme power reduction.◦       ..

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