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Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme1
Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme2
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Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme1
Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme2
Home Projects Matlab Digital Image Processing Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme
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Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs
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Approximate DCT Design for Video Encoding Based on Novel Truncation Scheme

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SKU: VLSI - Digital Signal Processing Categories: Digital Image Processing, Projects Tag: VLSI - Digital Signal Processing
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Description

Abstract

              Discrete cosine transform (DCT) is significantly important and widely utilized in signal compression. Through DCT, spatial signals can be converted to frequency domain, in which each signal is decomposed of components at different frequencies. For natural signals, most of the energy is concentrated in the low-frequency regions.

            In the existing system, it is being reduced the computation cost of DCT by truncating a couple of least significant bits (LSB), most significant bits (MSB), and zero columns. First, considering that the contribution of LSBs is weakened because of the final right shift operation, we have eliminated the computation process for some LSBs. For the addition of the remaining LSBs, a parallel carry propagation adder is proposed to reduce the calculation latency. Second, owing to the phenomenon that high-frequency components are quite small in natural scenes, a couple of MSBs are selectively truncated according to their positions. In the proposed system, design of an advanced model of parallel DCT with iterative looping structure is used.

            The benefit of 32 bit iterative DCT improves the resolution of the processing elements for the input image. The structure utilizes low power principle and finally transform the image data with reduced errors. Simulation results are shown in MODELSIM & XILINX ISE, the language use for the programming is Low power principles in VHDL behavioral model.

Proposed system

               In the proposed system, design of an advanced model of parallel DCT with iterative looping structure is used. The benefit of 32 bit iterative DCT improves the resolution of the processing elements for the input image. The structure utilizes low power principle and finally transform the image data with reduced errors. Simulation results are shown in MODELSIM & XILINX ISE, the language use for the programming is Low power principles in VHDL behavioral model.

Solution Statement

  • Iterative DCT produces reduced processing time,
  • High resolution
  • Error free

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