Python
Abstract
◦ Clock networks consume large amounts of dynamic power,Clock gating is a common method for dynamic power reduction, and XOR self-gating is one of the useful clock gating methods for reducing meaningless clock toggling to provide extreme power reduction.
◦ In the Existing system, Design of test friendly architecture is evaluated in which the ATPG test is done using the data selectable self gating technique
◦ In the proposed system 4 types of Test pattern generation test is completely implemented. The test such as checker board test, pattern test, pseudorandom test., marching test have been evaluated to perform the post silicon validation completely.
Proposed system
◦ In the proposed system 4 types of Test pattern generation test is completely implemented. The test such as checker board test, pattern test, pseudorandom test., marching test have been evaluated to perform the post silicon validation completely.
Solution Statement
◦ Four highly strong testing is performed.
◦ Benchmark circuit is tested after the ATPG
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