RingNet: A Memory-Oriented Network-On-Chip

Existing system

              In the existing system design of novel NoC architecture called RingNet that is well-suited to the features of contemporary FPGAs. Among other NoC architectures developed for FPGAs, RingNet stands out with communication through a central memory and traffic load controlled by the recipient.

Propose system

              In the proposed design to improve the performance of processing elements when deal with multiple clock for inter domain translations a novel method called Reconfigurable Multi-Clock Ring Net ( RM-Ring Net) is developed. The proposed architecture enable the system adapt with any kind of FPGA devices and suitable for Multi code devices also. The extension of the work focus on developing the RM-Ring Net into MpSoc platform and can be implemented in a Xilinx FPGA for further validation.