Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs
Product Description
Synopsis
Three dimensional integration is one of the promising solutions to check the bare 3D integrated circuits before utilizing in the applications. In the existing system design of an heterogeneous architecture is being evaluated using low power silicon redundancy schemes. The technique is based on two optimal coding-based redundancy schemes, used in combination, which allows minimizing the complexity of a redundancy technique in heterogeneous systems.
The existing technique reduce the interconnect power consumption. In the proposed system, an automated model of reconfigurable 3D soc testing platform is created in which a design of adjustable SRAM is implemented first. The data in the sram is encoded using Euclidean principle. Further the SRAM is tested with three different test patterns such as Pseudorandom Test, Marching Test and Checker board test. The proposed simulation is executed and verified in MODELSIM / QUARTUS II and implemented partial configuration in XILINX ISE.
Proposed system
In the proposed system, an automated model of reconfigurable 3D soc testing platform is created in which a design of adjustable SRAM is implemented first. The data in the sram is encoded using Euclidean principle. Further the SRAM is tested with three different test patterns such as Pseudorandom Test, Marching Test and Checker board test. The proposed simulation is executed and verified in MODELSIM / QUARTUS II and implemented partial configuration in XILINX ISE.
Solution Statement
- Automated Self Test mechanism is implemented
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